1. Field of the Invention
The present disclosure generally relates to the field of semiconductor manufacturing, and, more particularly, to forming contact levels having a dielectric material system that are formed on the basis of differently stressed dielectric materials.
2. Description of the Related Art
Semiconductor devices, such as advanced integrated circuits, typically contain a great number of circuit elements, such as transistors, capacitors, resistors and the like, which are usually formed in a substantially planar configuration on an appropriate substrate having formed thereon a semiconductor layer. Due to the high number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements may generally not be established within the same level on which the circuit elements are manufactured, but require a plurality of additional “wiring” layers, which are also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, which are also referred to as “vias,” that are filled with an appropriate metal and provide the electrical connection between two neighboring stacked metallization layers.
Furthermore, the circuit elements are typically embedded in a dielectric material system, which provides the desired degree of passivation and robustness of the circuit elements prior to forming the complex metallization system. Hence, an appropriate contact regime or contact structure is implemented in the dielectric material system that passivates the circuit elements and that will also be referred to herein as an interlayer dielectric material. Due to the continuous shrinkage of the critical dimensions of the circuit elements, and thus due to the reduced lateral pitch of closely spaced circuit elements, the contact structure of the semiconductor device, which may be considered as an interface connecting the circuit elements of the device level with the metallization system, has to be adapted to the reduced feature sizes in the device level and the metallization system. For this reason, very sophisticated patterning strategies may have to be applied in order to provide the contact elements with the required density and with appropriate reduced dimensions, at least at the device level side, in order to appropriately connect to the contact regions, such as drain and source regions, gate electrode structures and the like, without contributing to pronounced leakage current paths and even short circuits and the like. In many conventional approaches, the contact elements or contact plugs are typically formed by using a tungsten-based metal together with an interlayer dielectric stack that is typically comprised of silicon dioxide in combination with an etch stop material, such as a silicon nitride material. Due to the very reduced critical dimensions of the circuit elements, such as the transistors, the respective contact elements have to be formed on the basis of contact openings with an aspect ratio which may be as high as approximately 8:1 or more, wherein a diameter of the contact openings may be 0.1 μm or significantly less for transistor devices of, for instance, the 65 nm technology node. In even further sophisticated approaches, and in very densely packed device regions, the width of the contact openings may be 50 nm and less.
In addition to establishing the vertical interconnects between the circuit elements and the complex metallization system, the contact level of sophisticated semiconductor devices may be further used for enhancing performance of transistor elements by implementing a strain-inducing mechanism. It is well known that performance of field effect transistors may significantly depend on the resistivity of the channel region of the transistors. For this reason, the reduction of the channel length has been one dominant design criterion in order to reduce the overall resistivity of the channel regions. The reduction of the channel length typically, however, requires an increased capacitive coupling in order to maintain the desired degree of controllability of the current flow in the channel region. For this reason, the thickness of the gate dielectric material, typically comprised of silicon dioxide-based materials, has been reduced, which, however, may result in a significant increase of the static leakage currents caused by charge carriers that may directly tunnel through an extremely thin gate dielectric material. Upon implementing channel lengths of beyond 100 nm, other performance-enhancing mechanisms have been taken into consideration in order to provide superior channel conductivity for a given design channel length. It is well known that, for instance, silicon material may exhibit a significant variability of charge carrier mobility when provided in a strained state. Consequently, by appropriately selecting the strain conditions of the silicon channel material, the charge carrier mobility of electrons and/or holes may be efficiently increased, thereby also achieving a significantly higher drive current capability and switching speed of the transistors. As a consequence, in the past, a plurality of efficient strain-inducing mechanisms have been developed, wherein one promising approach is based on the provision of highly stressed dielectric materials in the interlayer dielectric material system of the semiconductor device. For example, silicon nitride material, which is a well-established etch stop material used in interlayer dielectric material systems, may be efficiently provided with a high internal stress level by appropriately selecting the process parameters of the corresponding plasma enhanced chemical vapor deposition (CVD) process. For example, silicon nitride material may be deposited with a high internal compressive stress level of up to 2 GPa or even higher, which may result in significant performance gain of P-channel transistors. Similarly, silicon nitride material may also be efficiently deposited with a high internal tensile stress level of up to 2 GPa, thereby providing the possibility of significantly increasing performance of N-channel transistors. Generally, providing the etch stop material of the interlayer dielectric material system with a high internal stress level represents an efficient strain-inducing mechanism since these materials may be positioned closely to the actual transistor elements, that is, above and laterally adjacent to the gate electrode structures and on the drain and source regions. Upon further shrinkage of the critical dimensions, however, the lateral pitch between gate electrode structures may also have to be reduced, in particular in densely packed device areas, such as memory areas of complex semiconductor devices and the like, which may result in a very sophisticated surface topography upon depositing the highly stressed dielectric materials. Since the finally obtained magnitude of the strain in the corresponding channel regions may significantly depend on the internal stress level of the dielectric materials and the amount of these materials that may be positioned in close proximity to the transistor elements, typically, the deposition processes have been optimized so as to increase the internal stress level since the amount of stressed material is substantially determined by the overall device geometry. It turns out, however, that deposition recipes designed to provide superior internal stress levels may not at the same time provide high gap fill capabilities during the deposition process, which may result in significant deposition-related irregularities, such as voids and the like, which may result in pronounced device failures upon forming the contact elements in the interlayer dielectric material system. In particular, in sophisticated process strategies in which a tensile stressed dielectric material may be selectively placed above and adjacent to N-channel transistors and a compressively stressed dielectric material is positioned selectively above and adjacent to P-channel transistors, increased yield losses have been observed due to a pronounced increase of catastrophic contact failures.
With reference to FIGS. 1a-1d, a sophisticated dual stress liner approach, i.e., a strategy in which tensile stressed and compressive stressed dielectric materials may be selectively positioned in the vicinity of N-channel transistors and P-channel transistors, respectively, will now be described in more detail in order to identify possible mechanisms which may cause the significant increase in yield loss.
FIG. 1a schematically illustrates a top view of a semiconductor device 100 in a very advanced manufacturing stage. The semiconductor device 100 comprises a first device area 110B, which may be understood hereinafter as an area in which a certain type of strain may be required for enhancing performance of any transistor elements provided within the device area 110B. For example, in this area, a compressive strain or a tensile strain may result in superior performance of the corresponding transistor elements. Similarly, the semiconductor device 100 comprises a second device area 110A in which a certain type of strain may also result in superior performance of circuit elements formed therein, wherein the strain required in the area 110A is inverse with respect to the type of strain required in the device area 110B. In the device area 110B, one or more semiconductor regions or active regions 102C, 102D are provided, which are to be understood as semiconductor regions in and above which one or more transistor elements are formed, wherein, for convenience, gate electrode structures 120B of any such transistors are illustrated in FIG. 1a. As previously discussed, the current flow of a field effect transistor is controlled by a gate electrode structure, such as the structure 120B, while the drive current capability may also depend on the overall channel conductivity, as is also discussed above. Generally, the transistor performance and in particular the channel conductivity may depend on complex dopant profiles in the drain and source regions, the dopant concentration in the channel region, the length thereof and the strain level induced therein. Consequently, performance of any transistors provided in the active regions 102C, 102D may be enhanced by providing an interlayer dielectric material system 130 that may induce an appropriate strain component, as discussed above. In the device configuration as shown in FIG. 1a, an isolation region 1021, for instance in the form of a shallow trench isolation and the like, is formed so as to separate the active regions 102C, 102D, thereby electrically insulating the active regions 102C, 102D, if required.
Similarly, the device area 110A may comprise one or more active regions 102A, 102B which may require a specific type of strain-inducing material in order to enhance performance of corresponding transistors provided in the active regions 102A, 102B. Any such transistors may be represented by gate electrode structures 120A, 120C, which may be positioned in close proximity in accordance with sophisticated design rules of the device 100. In the example shown, the interlayer dielectric material system 130 may thus provide a type of strain in the active regions 102A, 102B that is inverse to the type of strain induced in the active regions 102C, 102D.
It should be appreciated, however, that, in other device areas, the active regions 102A, 102B may represent active regions of transistors of different conductivity type and thus the material system 130 may be appropriately configured to provide these different types of strain for the active regions 102A, 102B.
Moreover, as explained before, sophisticated contact elements 131 may have to be provided so as to connect to the circuit elements and thus to the corresponding active regions 102A, 102B, 103C, 102D in accordance with the overall requirements of the device 100. It has been observed, however, that, in particular in the context of critical dimensions of less than 100 nm and in densely packed device regions, such as the device area 110A, significant contact failures are generated which are believed to be caused by any short circuits or leakage paths connecting adjacent contact elements 131 across the isolation region 1021, as is indicated by the leakage path 131L.
FIG. 1b schematically illustrates a cross-sectional view of the semiconductor device 100 along the line Ib as illustrated in FIG. 1a. In the manufacturing stage shown, the semiconductor device 100 comprises a substrate 101, such as a silicon substrate or any other appropriate semiconductor carrier material which is appropriate for providing thereon a semiconductor layer (not shown), such as a silicon layer and the like. It should be noted that the corresponding semiconductor layer may be divided into the various active regions, such as the regions 102A, 102B, 102C, 102D, as shown in FIG. 1a, by the isolation region 1021. It should be appreciated, however, that a crystalline semiconductor material may be provided below the isolation region 102I, while in a silicon-on-insulator (SOI) configuration, the isolation structure 102I may connect to a buried insulating material, which may also be provided below the active regions 102A, 102B, 102C, 102D shown in FIG. 1a. Moreover, in the manufacturing stage shown, the gate electrode structure 120B may be provided in the first device area 110B, while the gate electrode structures 120A, 120C are provided in the second device area 110A. The gate electrode structures 120A, 120B, 120C typically comprise an electrode material 121, such as a polycrystalline silicon material and the like, possibly in combination with a metal-containing portion 123, for instance in the form of a metal silicide, and a gate dielectric material 122 which may, however, not be provided above the isolation region 102I, depending on the process strategy used for forming the gate electrode structures. Furthermore, a sidewall spacer structure 124 may be provided so as to laterally enclose the electrode material or materials 121, 123. It should be appreciated, however, that, in very sophisticated approaches, the gate electrode structures 120A, 120B, 120C may also comprise high-k dielectric materials in combination with metal-containing electrode materials. Furthermore, in the manufacturing stage shown, a portion of the material system 130 may be provided in the form of a highly stressed dielectric layer 132, such as a silicon nitride material, in combination with an etch stop layer 133, such as a silicon dioxide material. In the example shown, the internal stress level of the material 132 may be appropriate so as to enhance performance of any transistors provided in the second device area 110A, wherein, for instance, a tensile stress level may enhance performance of N-channel transistors, while a compressive stress level may enhance performance of P-channel transistors.
The semiconductor device 100 as shown in FIG. 1b may be formed on the basis of the following process techniques. In an early manufacturing stage, the basic semiconductor layer formed above the substrate 101 may be divided into active regions by providing the isolation region 102I, as is, for instance, shown in FIG. 1a. To this end, sophisticated lithography, etch, deposition and planarization techniques may be applied in order to define the lateral size and position of active regions 102A, 102B, 102C, 102D, as shown in FIG. 1a. Next, the gate electrode structures 120A, 120B, 120C may be formed by providing appropriate materials for the gate dielectric layer 122, the electrode material 121 and possibly any further materials, such as high-k dielectric materials, metal-containing electrode materials, hard mask materials and the like. Based on a corresponding layer stack, complex lithography and patterning techniques may be applied in order to obtain the gate electrode structures with a desired gate length, i.e., in FIG. 1b, the horizontal extension of the electrode material 121, and with a desired lateral pitch of the gate electrode structures, in order to comply with the overall design criteria. If required, additional strain-inducing mechanisms may be implemented, for instance, by incorporating an embedded strain-inducing semiconductor material in at least some of the active regions 102A, 102B, 102C, 102D (FIG. 1a) and the like. Thereafter, the processing may be continued by forming drain and source regions (not shown) in combination with the sidewall spacer structure 124, which may be accomplished by using well-established masking regimes and implantation techniques for incorporating a desired type and concentration of dopant species into the corresponding active regions. After any anneal processes during which the final dopant profile may be adjusted and any implantation-induced damage may be re-crystallized, a metal silicide may be formed in the active regions and possibly in the gate electrode structures 120A, 120B, 120C, as indicated by 123, which may be accomplished by any well-established silicidation technique.
It should be appreciated that a plurality of complex etch and cleaning steps may be required during the manufacturing sequence for forming the basic transistor configuration including the gate electrode structures 120A, 120B, 120C, which may result in a pronounced material loss, in particular in the isolation region 102T, thereby forming corresponding recesses 102R. For example, a plurality of efficient cleaning recipes may be required, for instance, after any sophisticated etch techniques, resist removal processes and the like, in which, frequently, hydrofluoric acid and other efficient wet chemical solutions are applied which, however, may also efficiently remove silicon dioxide material, thereby increasingly contributing to a significant material loss in the isolation region 102I so that a pronounced surface topography may be created in the isolation region 102I, while a corresponding interaction of these processes with a semiconductor material, such as a silicon material, may be significantly less pronounced. Consequently, upon completing the basic transistor configuration, a pronounced surface topography may be obtained, in particular in the densely packed device area 110A due to the closely spaced gate electrode structures 120A, 120C, wherein this topography may further be increased due to the creation of the recesses 102R. Consequently, during the further processing in forming the complex material system 130, extremely sophisticated conditions may be encountered in the device area 110A. As previously discussed, during the deposition of the dielectric material 132, the process parameters may be appropriately adapted to as to obtain a very high internal stress level, which, however, may be associated with a reduced gap fill capability, thereby imposing specific restrictions with respect to layer thickness. Generally, the thickness of the layer 132 is selected so as to obtain a moderately high amount of highly stressed material while also enabling the deposition and patterning of a further highly stressed dielectric material and the patterning thereof during the further processing. For example, the highly stressed dielectric material 132 may be provided with a thickness of 30-80 nm, depending on the critical dimensions of the gate electrode structures 120A, 120C. Thereafter, the etch stop layer 133, for instance provided in the form of a silicon dioxide material, may be deposited by well-established deposition techniques. Next, an etch mask 103, such as a resist mask, may be provided so as to mask the second device area 110A while exposing the first device area 110B. Thereafter, an etch process 104 may be applied so as to first etch through the etch stop material 133 and subsequently provide an appropriate etch chemistry for removing the material 132, which may be accomplished on the basis of well-established plasma assisted etch recipes. It should be appreciated that, if desired, a thin etch stop material (not shown) may be provided below the highly stressed dielectric material 132 in order to enhance controllability of the etch process 104. After the selective removal of the layers 133 and 132 in the device area 110B, the processing is continued by removing the etch mask 103.
FIG. 1c schematically illustrates a cross-sectional view of the device 100 in a further advanced manufacturing stage. As illustrated, a further highly stressed dielectric material 134 is formed above the gate electrode structures 120A, 120B, 120C. As previously discussed, the layer 134 has an internal stress level that is inverse with respect to the stress of the dielectric material 132. For the deposition of the dielectric material 134, the same criteria apply as previously explained, so that, typically, process parameters are selected such that a high internal stress level is obtained while, however, achieving a reduced gap fill capability. Hence, due to the pronounced surface topography in the device area 110A, an increased probability of creating deposition-related irregularities may exist, thereby forming a void 134V between the closely spaced gate electrode structures 120A, 120C.
FIG. 1d schematically illustrates the device 100 in a further advanced manufacturing stage. In this stage, a further etch mask 106, such as a resist mask, is provided so as to cover the gate electrode structure 120B, while exposing the device area 110A. On the basis of the etch mask 106, a further plasma assisted etch process 105 is performed in order to remove the material layer 134 from above the device area 110A. To this end, a plurality of well-established plasma assisted etch recipes are available, for instance for removing silicon nitride material selectively with respect to silicon dioxide. Although it is highly desirable to substantially completely remove the material layer 134 from the device area 110A, it has been observed that, for sophisticated semiconductor devices, in particular in the device area 110A, significant portions of the material layer 134 may be preserved during the process 105, thereby possibly maintaining the void 134V, or at least a significant portion thereof. Consequently, upon depositing a further dielectric material, such as a silicon dioxide material, the void 134V or a portion thereof may still remain within the material system 130, which may result in significant device failure upon further processing, i.e., upon forming the contact elements 131 (FIG. 1a). That is, upon forming corresponding contact openings in the material system 130, a connection to the voids 134V may also be created and, upon refilling the contact openings with an appropriate contact material, such as tungsten, by CVD-like processes, tungsten material may be efficiently deposited into the void 134V, which may result in a highly conductive path. In some cases, the void 134V may extend from one contact element 131 to another contact element 131 provided in two different active regions, thereby establishing a conductive path, which may result in severe leakage currents or even short circuits, which may not be compatible with performance characteristics of the device 100 or which may even result in a catastrophic contact failure.
Without intending to restrict the present application to the following explanation, it is believed that the incomplete removal of the material 134 during the etch process 105 may be caused by the limited selectivity of the etch chemistry, which may have its deeper reasons in the pronounced surface topography. That is, during the etch process 105, the gas flow between the closely spaced gate electrode structures 120A, 120C may be reduced compared to less critical device areas so that a reduced etch rate may result in critical device areas, which may finally result in significant material residues of the layer 134 between the closely spaced gate electrode structures 120A, 120C. Increasing the total process time during the plasma assisted etch process 105 is, however, a less desirable option since, in this case, the etch stop layer 133 may be attacked in less critical device areas, such as above the gate electrode structures 120A, 120C, which may finally result in a significant material removal of the underlying highly stressed dielectric material 132. On the other hand, increasing the thickness of the etch stop material 133 is less than desirable since, in this case, it may be extremely difficult to remove the etch stop material 133 during the etch process 104 (FIG. 1b), which may thus result in significant non-uniformities upon removing the material 132 from above the device area 110B. Providing the etch stop layer 133 with a sufficient thickness after the removal of the layer 132 from above the device area 110B may, however, result in significantly reduced strain in the area 110B, since then the material layer 134 may have to be formed on the relatively thick etch stop layer 133.
Moreover, reducing the thickness of one or both of the layers 132 and 134 in order to provide a reduced probability of creating a void may also result in a significant loss of performance due to the reduced magnitude of strain induced in the corresponding device areas 110A, 110B, respectively.
In other approaches, the deposition-related irregularities may be accepted and the incorporation of a conductive material into the void 134V may be hindered by providing a silicon dioxide liner material in the contact opening prior to depositing the contact metal. In this case, an appropriate “sealing” of the contact opening may require moderately thick oxide liners or may be successfully applied for voids of reduced size so that, nevertheless, a significant risk of creating leakage paths may still be present. Furthermore, providing a moderately thick silicon dioxide liner in the contact openings may significantly reduce the critical dimensions thereof, which may thus result in a reduced conductivity, in particular when extremely scaled semiconductor devices are considered.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.